Fault-tolerant gates via homological product codes
APA
(2018). Fault-tolerant gates via homological product codes. Perimeter Institute. https://pirsa.org/18100046
MLA
Fault-tolerant gates via homological product codes. Perimeter Institute, Oct. 03, 2018, https://pirsa.org/18100046
BibTex
@misc{ pirsa_PIRSA:18100046, doi = {10.48660/18100046}, url = {https://pirsa.org/18100046}, author = {}, keywords = {Quantum Information}, language = {en}, title = {Fault-tolerant gates via homological product codes}, publisher = {Perimeter Institute}, year = {2018}, month = {oct}, note = {PIRSA:18100046 see, \url{https://pirsa.org}} }
I will present a method for the implementation of a universal set of fault-tolerant logical gates using homological product codes. In particular, I will show how one can fault-tolerantly map between different encoded representations of a given logical state, enabling the application of different classes of transversal gates belonging to the underlying quantum codes. This allows for the circumvention of no-go results pertaining to universal sets of transversal gates and provides a general scheme for fault-tolerant computation while keeping the stabilizer generators of the code sparse.